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ltc3609 1 3609fb typical application features applications description 32v, 6a monolithic synchronous step-down dc/dc converter the ltc ? 3609 is a high eficiency, monolithic synchronous step-down dc/dc converter that can deliver up to 6a output current from a 4v to 32v (36v maximum) input supply. it uses a valley current control architecture to deliver very low duty cycle operation at high frequency with excellent transient response. the operating frequency is selected by an external resistor and is compensated for variations in v in and v out . the ltc3609 can be conigured for discontinuous or forced continuous operation at light load. forced continu- ous operation reduces noise and rf interference while discontinuous mode provides high eficiency by reducing switching losses at light loads. fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an o ptional short-circuit shutdown timer. soft-start capability for sup- ply sequencing is accomplished using an external timing capacitor. the regulator current limit is user prog rammable. a power good output voltage monitor indicates when the output is in regulation. the ltc3609 is available in a compact 7mm 8mm qfn package. n 6a output current n wide v in range = 4v to 32v (36v maximum) n internal n-channel mosfets n true current mode control n optimized for high step-down ratios n t on(min) 100ns n extremely fast transient response n stable with ceramic c out n 1% 0.6v voltage reference n power good output voltage monitor n adjustable on-time/switching frequency n adjustable current limit n programmable soft-start n output overvoltage protection n optional short-circuit shutdown timer n low shutdown i q : 15a n available in a 7mm 8mm 52-pin qfn package n point of load regulation n distributed power systems 1.2h 4.7f 10fx3 v in 4v to 32v v out 2.5v6a 3609 ta01a 187k 0.1f i on v in sw boost run/ssi th v on v out sgnd intv cc fcb pgnd v fb v rng 0.22f 100fx2 15.8k ltc3609 1000pf extv cc pgood 30.1k9.53k 100pf load current (a) 0.01 efficiency (%) power loss (mw) 80 90 3609 ta 01b 70 0 5040 30 20 10 60 0.1 1 10 100 1000100 1 10 10000 v out = 2.5v extv cc = 5v v in = 12v v in = 25v power loss efficiency high ef?ciency step-down converter ef?ciency and power loss vs load current l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6100678, 6580258, 5847554, 6304066. downloaded from: http:///
ltc3609 2 3609fb pin configuration absolute maximum ratings input supply voltage (sv in , pv in , i on ) ....... 36v to C0.3v boosted topside driver supply voltage (boost) ................................................ 42v to C0.3v sw voltage ............................................ 36v to C0.3v intv cc , extv cc , (boost C sw), run/ss, pgood voltages ...................................... 7v to C0.3v fcb, v on , v rng voltages ............ intv cc + 0.3v to C0.3v i th , v fb voltages ....................................... 2.7v to C0.3v operating junction temperature range (notes 2, 4) ........................................ C40c to 125c storage temperature range ................... C55c to 125c (note 1) top view wkg package 52-lead (7mm s 8mm) qfn multipad pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 40 pgnd39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 pgnd 33 sw 32 intv cc 31 intv cc 30 sv in 29 extv cc 28 nc27 sgnd sgnd 15 pgood 16 v rng 17 i th 18 fcb 19 sgnd 20 nc 21 i on 22 v fb 23 nc 24nc 25 sgnd 26 52 pv in 51 pv in 50 pv in 49 pv in 48 pv in 47 sw46 sw 45 sw 44 sw 43 sw 42 sw 41 sw 53 pv in 55 sw 54 sgnd t jmax = 125c, ja = 29c/w order information lead free finish tape and reel part marking* package description temperature range ltc3609ewkg#pbf ltc3609ewkg#trpbf ltc3609wkg 52-lead (7mm 8mm) plastic qfn C40c to 125c ltc3609iwkg#pbf ltc3609iwkg#trpbf ltc3609wkg 52-lead (7mm 8mm) plastic qfn C40c to 125c consult ltc marketing for parts speciied with wider operating temperature ranges. *the temperature gr ade is identiied by a label on the shipping contain er. consult ltc marketing for information on non-standard lead based inish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc3609 3 3609fb symbol parameter conditions min typ max units main control loop sv in operating input voltage range 4 32 v i q input dc supply current normal shutdown supply current 900 15 2000 30 a a v fb feedback reference voltage i th = 1.2v (note 3) C40c to 85c C40c to 125c l 0.594 0.590 0.600 0.600 0.606 0.610 v v ?v fb(linereg) feedback voltage line regulation v in = 4v to 30v, i th = 1.2v (note 3) 0.002 %/v ?v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) C0.05 C0.3 % i fb feedback input current v fb = 0.6v C5 50 na g m(ea) error ampliier transconductance i th = 1.2v (note 3) l 1.4 1.7 2 ms v fcb forced continuous threshold l 0.54 0.6 0.66 v i fcb forced continuous pin current v fcb = 0.6v C1 C2 a t on on-time i on = 60a, v on = 1.5v i on = 60a, v on = 0v 220 280 110 340 ns ns t on(min) minimum on-time i on = 180a, v on = 0v 60 100 ns t off(min) minimum off-time i on = 30a, v on = 1.5v 320 500 ns i valley(max) maximum valley current v rng = 0v, v fb = 0.56v, fcb = 0v v rng = 1.2v, v fb = 0.56v, fcb = 0v l l 4 6 9 14 a a i valley(min) maximum reverse valley current v rng = 0v, v fb = 0.64v, fcb = 0v v rng = 1.2v, v fb = 0.64v, fcb = 0v 4 7 a a ?v fb(ov) output overvoltage fault threshold 7 10 13 % v run/ss(on) run pin start threshold l 0.8 1.5 2 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 4 4.5 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 4.2 v i run/ss(c) soft-start charge current v run/ss = 0v C0.5 C1.2 C3 a i run/ss(d) soft-start discharge current v run/ss = 4.5v, v fb = 0v 0.8 1.8 3 a v in(uvlo) undervoltage lockout v in falling l 3.4 3.9 v v in(uvlor) undervoltage lockout release v in rising l 3.5 4 v r ds(on) top switch on-resistance bottom switch on-resistance 18 13 27 22 m m electrical characteristics the l denotes the speci?cations which apply over the full operating junction temperature range, otherwise speci?cations are at t a = 25c. v in = 15v unless otherwise noted. downloaded from: http:///
ltc3609 4 3609fb electrical characteristics the l denotes the speci?cations which apply over the full operating junction temperature range, otherwise speci?cations are at t a = 25c. v in = 15v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d 29c/w) ( ja is simulated per jesd51-7 high effective thermal conductivity test board). jc = 1c/w ( jc is simulated when heat sink is applied at the bottom of the package). note 3: the ltc3609 is tested in a feedback loop that adjusts v fb to achieve a speciied error ampliier output voltage (i th ). the speciication at 85c is not tested in production. this speciication is assured by design, characterization, and correlation to testing at 125c. note 4: the ltc3609 is tested under pulsed load conditions such that t j t a . the ltc3609e is guaranteed to meet speciications from 0c to 125c junction temperature. speciications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3609i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these speciications is determined by speciic operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. symbol parameter conditions min typ max units internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v l 4.7 5 5.5 v ?v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v C0.1 2 % v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising l 4.5 4.7 v ?v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 5v 150 300 mv ?v extvcc(hys) extv cc switchover hysteresis 500 mv pgood output ?v fbh pgood upper threshold v fb rising 7 10 13 % ?v fbl pgood lower threshold v fb falling C7 C10 C13 % ?v fb(hys) pgood hysteresis v fb returning 1 2.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v transient response transient response (discontinuous mode) start-up load step 0a to 5av in = 25v v out = 2.5v fcb = 0vfigure 6 circuit 3609 g01 20s/div v out 200mv/div i l 5a/div i load 5a/div load step 1a to 6av in = 25v v out = 2.5v fcb = intv cc figure 6 circuit 3609 g02 20s/div v out 200mv/div i l 5a/div i load 5a/div v in = 12v v out = 2.5v r load = 0.5 figure 6 circuit 3609 g03 40ms/div run/ss 2v/div v out 1v/div i l 5a/div typical performance characteristics downloaded from: http:///
ltc3609 5 3609fb load current (a) 0.01 efficiency (%) 70 80 10 3609 g04 60 0 5040 30 20 10 0.1 1 100 90 v in = 12v frequency = 550khz v out = 5v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v out = 1v input voltage (v) 5 80 efficiency (%) 85 90 95 100 8 14 17 11 29 3609 g05 32 20 26 23 i load = 1a i load = 6a fcb = 5vfigure 6 circuit 5 8 14 17 11 29 32 20 26 23 input voltage (v) frequency (khz) 500 3609 g06 450400 650600 550 fcb = 0vfigure 6 circuit i load = 1a i load = 6a load current (a) ?v out (%) 3609 g08 ?0.80 ?0.60 ?0.40 ?0.20 0.600.40 0.20 0 0.80 figure 6 circuit 0 2 4 6 8 load current (a) 0 i th voltage (v) 1.0 1.5 3609 g09 0.5 0 4 2 6 8 2.52.0 continuousmode discontinuousmode figure 6 circuit load current (a) 0 0 frequency (khz) 100 200 300 400 500 600 700 2 4 6 3609 g07 8 continuous mode discontinuous mode ef?ciency vs load current ef?ciency vs input voltage frequency vs input voltage frequency vs load current load regulation i th voltage vs load current typical performance characteristics i th voltage (v) 0 C10 load current (a) C5 0 5 10 15 0.5 1.0 1.5 2.0 3609 g10 2.5 v rng = 1.2v v rng = 1v v rng = 0.7v i on current (a) 1 10 on-time (ns) 100 1000 10000 10 100 3609 g11 v von = 0v v on voltage (v) 0 on-time (ns) 400 600 3609 g12 200 0 1 2 3 1000 i on = 30a 800 load current vs i th voltage at different v rng on-time vs i on current on-time vs v on voltage downloaded from: http:///
ltc3609 6 3609fb typical performance characteristics input voltage (v) 4 maximum valley current (a) 10 3609 g17 0 2 4 6 8 12 20 28 36 run/ss voltage (v) 1.65 0 maximum valley current limit (a) 3 6 9 12 15 1.90 2.15 2.65 2.90 3.15 3.40 2.40 3609 g15 figure 6 circuit temperature (c) C50 on-time (ns) 200 250 300 25 75 3609 g13 150100 C25 0 50 100 125 50 0 i ion = 30a v von = 0v v fb (v) 0 maximum valley current limit (a) 0.1 0.2 0.3 0.4 0.5 0.6 3609 g18 10 0 2 4 6 8 v rng voltage (v) 0.5 0 maximum valley current limit (a) 3 6 9 12 15 0.6 0.7 0.8 3609 g14 0.9 1.2 1.1 1.0 figure 6 circuit temperature (c) C50 C25 maximum valley current limit (a) 0 50 75 3609 g16 25 100 125 0 3 6 9 12 15 on-time vs temperature maximum valley current limit in foldback maximum valley current limit vs v rng voltage maximum valley current limit vs run/ss voltage maximum valley current limit vs temperature maximum valley current vs input voltage temperature (c) C50 C25 1.0 g m (ms) 1.4 2.0 0 50 75 3609 g20 1.2 1.8 1.6 25 100 125 input voltage (v) 0 input current (a) shutdown current (a) 800 1000 14001200 15 25 3609 g21 600400 5 10 20 30 200 0 3025 15 5 4035 20 10 0 extv cc open extv cc = 5v shutdown error ampli?er g m vs temperature input and shutdown currents vs input voltage temperature (c) C50 0.58 feedback reference voltage (v) 0.59 0.60 0.61 0.62 C25 0 25 50 3609 g19 75 100 125 feedback reference voltage vs temperature downloaded from: http:///
ltc3609 7 3609fb typical performance characteristics temperature (c) C50 C25 0 extv cc switch resistance () 4 10 0 50 75 3609 g23 2 86 25 100 125 temperature (c) C50 fcb pin current (a) C0.50 C0.25 0 25 75 3609 g24 C0.75C1.00 C25 0 50 100 125 C1.25C1.50 temperature (c) C50 C25 C2 run/ss pin current (a) 0 3 0 50 75 3609 g25 C1 21 25 100 125 pull-up current pull-down current intv cc load current (ma) 0 ?intv cc (%) 0.10 0.20 0.30 40 3609 g22 0 ?0.20 ?0.10?0.40 ?0.30 10 20 30 50 intv cc load regulation extv cc switch resistance vs temperature fcb pin current vs temperature run/ss pin current vs temperature run/ss pin current vs temperature undervoltage lockout threshold vs temperature temperature (c) C50 3.0 run/ss pin current (a) 3.5 4.0 4.5 5.0 C25 0 25 50 3609 g26 75 100 125 latchoff enable latchoff threshold temperature (c) C50 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 C25 0 25 50 3609 g27 75 100 125 frequency (khz) 400 0 i extvcc (ma) 10 25 3609 g28 5 2015 900 800 700 600 500 1000 v in = 24v i extvcc vs frequency load step 1a to 4av in = 24v v out = 12v fcb = 0vfigure 8 circuit 3609 g29 40s/div f = 500khz v out 200mv/div i l 5a/div load step ef?ciency vs load current load current (a) 0.01 efficiency (%) 80 10 3609 g30 50 7570 65 60 55 0.1 1 100 90 9585 v in = 24v frequency = 500khz dcm ccm figure 8 circuit downloaded from: http:///
ltc3609 8 3609fb pin functions pv in (pins 1, 2, 3, 4, 5, 6, 7, 48, 49, 50, 51, 52, 53): main input supply. decouple this pin to power pgnd with the input capacitance, c in . sw (pins 8, 33, 41, 42, 43, 44, 45, 46, 47, 55): switch node connection to the inductor. the (C) terminal of the bootstrap capacitor, c b , also connects here. this pin swings from a diode voltage drop below ground up to v in . nc (pins 9, 21, 24, 25, 28): no connection. sgnd (pins 10, 14, 15, 20, 26, 27, 54): signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. boost (pin 11): boosted floating driver supply. the (+) terminal of the bootstrap capacitor, c b , connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . run/ss (pin 12): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. v on (pin 13): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output volt- age or an external resistive divider from the output makes the on-time proportional to v out . the comparator input defaults to 0.7v when the pin is grounded and defaults to 2.4v when the pin is tied to intv cc . tie this pin to intv cc in high v out applications to use a lower r on value. pgood (pin 16): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. v rng (pin 17): current limit range input. the voltage at this pin adjusts maximum valley current and can be set from 0.7v to 1.2v by a resistive divider from intv cc . it defaults to 0.7v if the v rng pin is tied to ground which results in a typical 9a current limit. i th (pin 18): current control threshold and error ampli ier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). fcb (pin 19): forced continuous input. tie this pin to ground to force continuous synchronous operation at low load, to intv cc to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. i on (pin 22): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb (pin 23): error ampliier feedback input. this pin connects the error ampliier input to an external resistive divider from v out . extv cc (pin 29): external v cc input. when extv cc exceeds 4.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v in . sv in (pin 30): supply pin for internal pwm controller. intv cc (pins 31, 32): internal 5v regulator output. the driver and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 4.7f low esr tantalum or ceramic capacitor. pgnd (pins 34, 35, 36, 37, 38, 39, 40): power ground. connect this pin closely to the (C) terminal of c vcc and the (C) terminal of c in . downloaded from: http:///
ltc3609 9 3609fb functional diagram 0.7v 1.4v v rng C + C + C + C + C + i on v on i cmp 0.7v fcb extv cc sv in 1a r on v von i ion t on = (10pf) r s q 20k i rev s (0.5 to 2) 1v shdn switch logic on fcnt 0.6v C + 4.7v ov 1 240k 0.4v i th c ss ea ss 0.6v + C + C s 3.3 run/ss 3609 fd sgnd r1 run shdn pgndpgood v fb sw pv in c in boost m1m2 intv cc C + C + uv 0.54v ov 0.66v 6v 0.6v ref 5v reg r2 2.4v 17 13 22 19 29 30 11 nc 8, 33, 41, 42, 43, 44, 45, 46, 47, 55 1, 2, 3, 4, 5, 6, 7, 48, 49, 50, 51, 52, 53 31, 32 34, 35, 36, 37, 38, 39, 40 10, 14, 15, 20, 26, 27, 54 9, 21, 24, 25, 28 16 23 12 18 v out l1 c out c vcc + q1 q3 q4 q2 0.8v i thb q6 c b d b f 1.2a downloaded from: http:///
ltc3609 10 3609fb operation main control loop the ltc3609 is a high eficiency monolithic synchronous, step-down dc/dc converter utilizing a constant on-time, current mode architecture. it operates from an input voltage range of 4v to 32v/36v maximum and provides a regulated output voltage at up to 6a of output current. the internal synchronous power switch increases efi ciency and eliminates the need for an external schottky diode. in normal operation, the top mosfet is turned on for a ixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and initiating the next cycle. induc tor current is determined by sensing the voltage between the pgnd and sw pins using the bottom mosfet on-resistance. the voltage on the i th pin sets the comparator threshold corresponding to inductor valley current. the error ampli- ier, ea, adjusts this voltage by comparing the feedback signal v fb from the output voltage with an internal 0.6v reference. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. at light load, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev which then shuts off m2 (see func- tional diagram), resulting in discontinuous operati on. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinu- ous mode operation is disabled by comparator f when the fcb pin is brought below 0.6v, forcing continuous synchronous operation. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to main- tain regulation. the one-shot timer generates an on-time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor, r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback volt- age exits a 10% window around the regulation point. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down by clamp q3 to a 1v level set by q4 and q6. this reduces the inductor valley current level to one sixth of its maximum value as v fb approaches 0v. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2a current source to charge up an external soft-start capacitor, c ss . when this voltage reaches 1.5v, the controller turns on and begins switching, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft-start current limit is removed. intv cc /extv cc power power for the top and bottom mosfet drivers and mos t of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a loating bootstrap capacitor , c b . this capacitor is recharged from intv cc through an external schottky diode , d b , when the top mosfet is turned off. when the extv cc pin is grounded, an internal 5v low dropout regulator supplies the intv cc power from v in . if extv cc rises above 4.7v, the internal regulator is turned off, and an internal switch connects extv cc to intv cc . this allows a high eficiency source connected to extv cc , such as an external 5v sup- ply or a secondary output from the converter, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive. if the input voltage is low and intv cc drops below 3.5v, undervoltage lockout circuitry prevents the power switches from turning on. downloaded from: http:///
ltc3609 11 3609fb applications information the basic ltc3609 application circuit is shown on the front page of this data sheet. external component s election is primarily determined by the maximum load current. the ltc3609 uses the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency also determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient speciication. v on and pgood the ltc3609 has an open-drain pgood output that indicates when the output voltage is within 10 % of the regulation point. the ltc3609 also has a v on pin that allows the on-time to be adjusted. tying the v on pin high results in lower values for r on which is useful in high v out applications. the v on pin also provides a means to adjust the on-time to maintain constant frequency operation in applications where v out changes and to correct minor frequency shifts with changes in load current.v rng pin and i limit adjust the v rng pin is used to adjust the maximum inductor valley current, which in turn determines the maximum average output current that the ltc3609 can deliver. the maximum output current is given by: i out(max) = i valley(max) + 1/2 ?i l the i valley(max) is shown in the igure maximum valley current limit vs v rng voltage in the typical performance characteristics. an external resistor divider from intv cc can be used to set the voltage on the v rng pin from 0.7v to 1.2v, or it can be simply tied to ground force a default value equivalent to 0.7v. when setting current limit, ensure that the junc- tion temperature does not exceed the maximum rating of 125c. do not loat the v rng pin. operating frequency the choice of operating frequency is a tradeoff between eficiency and component size. low frequency operation improves eficiency by reducing mosfet switching los ses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc3609 applications is de- termined implicitly by the one-shot timer that controls the on-time, t on , of the top mosfet switch. the on-time is set by the current into the i on pin and the voltage at the v on pin according to: t v i pf on von ion = ( ) 10 tying a resistor r on from v in to the i on pin yields an on-time inversely proportional to v in . the current out of the i on pin is: i v r ion in on = for a step-down converter, this results in approximately constant frequency operation as the input supply varies: f v v r pf h out von on z = ( ) [ ] 10 to hold frequency constant during output voltage ch anges, tie the v on pin to v out or to a resistive divider from v out when v out > 2.4v. the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. in high v out applications, tying v on to intv cc so that the comparator input is 2.4v results in a lower value for r on . figures 1a and 1b show how r on relates to switching frequency for several common output voltages. downloaded from: http:///
ltc3609 12 3609fb applications information figure 1a. switching frequency vs r on (v on = 0v) figure 1b. switching frequency vs r on (v on = intv cc ) because the voltage at the i on pin is about 0.7v, the cur- rent into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. to correct for this error, an additional resistor r on2 con- nected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 0 7 = . changes in the load current magnitude will also cause frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the speciic application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 2a. place capacitance on the v on pin to ilter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 2b. r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3609 f01a v out = 3.3v v out = 1.5v v out = 2.5v r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3609 f01b v out = 3.3v v out = 12v v out = 5v downloaded from: http:///
ltc3609 13 3609fb applications information minimum off-time and dropout operation the minimum off-time, t off(min) , is the smallest amount of time that the ltc3609 is capable of turning on the bot- tom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v v t t t in min out on off min on ( ) ( ) = + a plot of maximum duty cycle vs frequency is shown in figure 3. setting the output voltage the ltc3609 develops a 0.6v reference voltage between the feedback pin, v fb , and the signal ground as shown in figure 6. the output voltage is set by a resistive divider according to the following formula: v out = 0.6v 1 + r2 r1 ?? ? ?? ? to improve the frequency response, a feed-forward c apaci- tor, c1, may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line.inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: i l = v out f l ?? ?? ?? ?? 1 ? v out v in ?? ? ?? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest eficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, eficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a speciied maximum, the inductance should be chosen according to: l = v out f i l(max) ?? ?? ?? ?? 1 ? v out v in(max) ?? ?? ?? ?? figure 3. maximum switching frequency vs duty cycle 2.01.5 1.0 0.5 0 0 0.25 0.50 0.75 3609 f03 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) figure 2. correcting frequency shift with load current changes c von 0.01f r von2 100k r von1 30k c c v out r c (2a) (2b) v on i th ltc3609 c von 0.01f r von2 10k q1 2n5087 r von1 3k 10k c c 3609 f02 v out intv cc r c v on i th ltc3609 downloaded from: http:///
ltc3609 14 3609fb applications information once the value for l is known, the type of inductor must be selected. high eficiency converters generally cannot afford the core loss found in low cost powdered iron cores. a variety of inductors designed for high current, low volt- age applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft and toko. c in and c out selection the input capacitance, c in , is required to ilter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. i i v v v v rms out max out in in out ? ( ) ? 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even signiicant de- viations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ?v out is approximately bounded by: v out i l esr + 1 8fc out ?? ? ?? ? since ?i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisied, the capacitance is adequate for iltering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum elect rolytic capacitors have signiicantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteris- tics but can have a high voltage coeficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signiicant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5f to 50f aluminum electrolytic capacitor with an esr in the range of 0.5 to 2. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. t op mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications an 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when in- ductor current reverses. the load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary downloaded from: http:///
ltc3609 15 3609fb applications information with changes in v in . tying the fcb pin below the 0.6v threshold forces continuous synchronous operation, al- lowing current to reverse at light loads and maintaining high frequency operation. in addition to providing a logic input to force continuous operation, the fcb pin provides a means to maintain a lyback winding output when the primary is operating in discontinuous mode. the secondary output v out2 is normally set as shown in figure 4 by the turns ratio n of the transformer. however, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then v out2 will droop. an external resistor divider from v out2 to the fcb pin sets a minimum voltage v out2(min) below which continuous operation is forced until v out2 has risen above its minimum: v out2(min) = 0.6v 1 + r4 r3 ?? ? ?? ? fault conditions: current limit and foldback the ltc3609 has a current mode controller which inh er- ently limits the cycle-by-cycle inductor current no t only in steady-state operation but also in transient. to further limit current in the event of a short circuit to gr ound, the ltc3609 includes foldback current limiting. if the output falls by more than 25%, then the maximum sense volt age is progressively lowered to about one sixth of its ful l value. intv cc regulator and extv cc connection an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the ltc3609. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7f tantalum or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. figure 4. secondary output loop and extv cc connection c sec 1f v out2 v out1 c out c in in4148 t1 1:n + + + 3609 f04 v in ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 gnd pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sgnd sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc 32 intv cc 31 sv in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 r4 optional extv cc connection5v < v out2 < 7v r3 downloaded from: http:///
ltc3609 16 3609fb applications information the extv cc pin can be used to provide mosfet gate drive and control power from the output or another external source during normal operation. whenever the extv cc pin is above 4.7v the internal 5v regulator is shut off and an internal 50ma p-channel switch connects the extv cc pin to intv cc . intv cc power is supplied from extv cc until this pin drops below 4.5v. do not apply more than 7v to the extv cc pin and ensure that extv cc v in . the following list summarizes the possible connections for extv cc : 1. extv cc grounded. intv cc is always powered from the internal 5v regulator. 2. e xtv cc connected to an external supply. a high ef iciency supply compatible with the mosfet gate drive require- ments (typically 5v) can improve overall eficiency. 3. ext v cc connected to an output derived boost network. the low voltage output can be boosted using a charge pump or lyback winding to greater than 4.7v. the system will start-up using the internal linear regulator until the boosted output supply is available. soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the lt c3609 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the ltc3609 into a low quiescent current shutdown (i q < 30a). releasing the pin allows an internal 1.2a current source to charge up the external timing capacitor, c ss . if run/ss has been pulled all the way to ground, there is a delay before start- ing of about: t v a c s f c delay ss ss = = ( ) 1 5 1 2 1 3 . . . / when the voltage on run/ss reaches 1.5v, the ltc3609 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/f, during which the load current is folded back until the output reaches 75% of its inal value. after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8a current then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 3.5v, then the controller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. t h e overcurrent protection timer requires that the so ft-start timing capacitor, c ss , be made large enough to guarantee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1f is more than suficient. overcurrent latchoff operation is not always needed or desired. load current is already limited during a short circuit by the current foldback circuitry and latchoff op- eration can prove annoying during troubleshooting. the feature can be overridden by adding a pull-up current greater than 5a to the run/ss pin. the additional cur- rent prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 5a is simple, but slightly increases shut- down current. connecting a resistor to intv cc as shown in figure 5b eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to pull run/ss above the 4.2v maximum threshold of the latchoff circuit and overcome the 4a maximum discharge current. downloaded from: http:///
ltc3609 17 3609fb applications information ef?ciency considerations the percent eficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the eficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3609 circuits: 1. dc i 2 r losses. these arise from the resistance of the internal resistance of the mosfets, inductor and pc board traces and cause the eficiency to drop at high output currents. in continuous mode the average output current lows through l, but is chopped between the top and bottom mosfets. the dc i 2 r loss for one mosfet can simply be determined by [r ds(on) + r l ] i o . 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signiicant at input voltages above 20v and can be estimated from: t ransition loss ? (1.7a C1 ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by supply- ing intv cc current through the extv cc pin from a high eficiency source, such as an output derived boost n etwork or alternate supply if available.4 . c in loss. the input capacitor has the dificult job of iltering the large rms input current to the regulat or. it must have a very low esr to minimize the ac i 2 r loss and suficient capacitance to prevent the rms current fr om causing additional upstream losses in fuses or batt eries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve eficiency, the input current is the best indicator of changes in eficiency. if you make a change and the input current decreases, then the eficiency has increased. if there is no change in input current, then there is no change in eficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in figure 6 will provide adequate compensation for most applications. for a detailed explanation of switching control loop theory see application note 76. 3.3v or 5v run/ss v in intv cc run/ss d1 (5a) (5b) d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3609 f05 2n7002 figure 5. run/ss pin interfacing with latchoff defeated downloaded from: http:///
ltc3609 18 3609fb applications information figure 6. design example: 5v to 32v input to 2.5v/6a at 550khz v out 2.5v at 6a gnd v in v in 5v to 32v c out1 100f x2 l1 1.2h c in 4.7f50v x2 + ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 sgnd gnd v out pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc intv cc intv cc 32 intv cc pgood 31 sv in v in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 3609 f06 c f 0.1f 50v r f1 1 c vcc 4.7f 6.3v extv cc c4 0.01f intv cc intv cc jp1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in c von 0.1f r19.53k 1% r pg1 100k r on 187k 1% r2 30.1k 1% r5 15.8k c c1 1000pf c c2 100pf v out c in : murata grm32er71h475k c out : murata grm435r60j107m l i : cdep851r2mc-50 keep power ground and signal ground separate. connect at one point. 2 design example as a design example, take a supply with the following speciications: v in = 5v to 32v (12v nominal), v out = 2.5v 5%, i out(max) = 6a, f = 550khz. first, calculate the timing resistor with v on = v out : r v v khz pf k on = ( )( )( ) = 2 5 2 4 550 10 187 . . and choose the inductor for about 40% ripple current at the maximum v in : l = 2.5v 550khz ( ) 0.4 ( ) 6a ( ) 1 ? 2.5v 32v ?? ? ?? ? = 1.8h selecting a standard value of 1.5h results in a maximum ripple current of: i l = 2.5v 550khz ( ) 1.5 h ( ) 1? 2.5v 12v ?? ? ?? ? = 2.4a next, set up v rng voltage and check the i limit . tying v rng to gnd will set the typical current limit to 9a, and tying v rng to 1.2v will result in a typical current around 14a. c in is chosen for an rms current rating of about 5a at 85c. the ceramic output capacitors are chosen for an esr of 0.002 to minimize output voltage changes due to inductor ripple current and load steps. the ripple volt- age is: ? v out(ripple) = ?i l(max) (esr) = (2.4a) (0.002) = 4.8mv and a 0a to 6a load step will only cause an output change of: ?v out(step) = ?i load (esr) = (6a) (0.002) = 12mv an optional 22f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 6. downloaded from: http:///
ltc3609 19 3609fb applications information how to reduce sw ringing as with any switching regulator, there will be voltage ring- ing on the sw node, especially for high input voltages. the ringing amplitude and duration is dependent on the switching speed (gate drive), layout (parasitic inductance) and mosfet output capacitance. this ringing contributes to the overall emi, noise and high frequency ripple. one way to reduce ringing is to optimize layout. a good layout minimizes parasitic inductance. adding rc snubbers from sw to gnd is also an effective way to reduce ringin g. finally, adding a resistor in series with the boost pin will slow down the mosfet turn-on slew rate to dampen ringing, but at the cost of reduced eficiency. note that since the ic is buffered from the high frequency transients by pcb and bondwire inductances, the ringing by itself is normally not a concern for controller reliability. pc board layout checklist when laying out a pc board follow one of the two sug- gested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, a multilayer board is recommended to help with heat sinking of power components. the ground plane layer should not have any traces and it should be as close as possible to the layer with the ltc3609. place c in and c out all in one compact area, close to the ltc3609. it may help to have some components on the bottom side of the board. keep small-signal components close to the l tc3609. ground connections (including ltc3609 sgnd and pgnd) should be made through immediate vias to the ground plane. use several larger vias for power components. use a compact plane for the switch node (sw) to im prove cooling of the mosfets and to keep emi down. use planes for v in and v out to maintain good voltage iltering and to keep power losses low. flood all unused areas on all layers with copper. flood- ing with copper reduces the temperature rise of power components. connect these copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 7. segregate the signal and power grounds. all small- signal components should return to the sgnd pin at one point, which is then tied to the pgnd pin. connect the input capacitor(s) , c in , close to the ic. this capacitor carries the mosfet ac current. keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. connect the intv cc decoupling capacitor, c vcc , closely to the intv cc and pgnd pins. connect the top driver boost capacitor, c b , closely to the boost and sw pins. connect the v in pin decoupling capacitor, c f , closely to the v in and pgnd pins. downloaded from: http:///
ltc3609 20 3609fb applications information figure 7. ltc3609 layout diagram c vcc c b d b c in ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc 32 intv cc 31 sv in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 r1 r2 c out v out c ss r c c c1 c c2 3609 f07 r f r on keep power ground and signal ground separate. connect at one point. downloaded from: http:///
ltc3609 21 3609fb load current (a) 0.01 efficiency (%) 80 10 3609 ta02c 50 7570 65 60 55 0.1 1 100 90 9585 v in = 3.6v frequency = 750khz load step 1a to 5av in = 3.6v v out = 1.5v fcb = 0v 3609 ta02b 20s/div v out 200mv/div i l 5a/div typical applications 3.6v input to 1.5v/6a at 750khz transient response ef?ciency vs load current v out 1.5v at 6a gnd v in v in 3.6v c out1 100f x2 l1 0.5h c in 4.7f50v x2 ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 sgnd gnd v out pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc intv cc intv cc 32 intv cc pgood 31 sv in v bias 5v 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 3609 ta02 c f 0.1f 50v c vcc 4.7f 6.3v extv cc c4 0.01f intv cc intv cc jp1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in c von 0.1f r140.2k 1% r pg1 100k r on 113k 1% r5 8.45k c c1 1500pf c c2 100pf v out c in : murata grm32er71h475k c out : murata grm435r60j167m l i : cdep850r5mc-125 2 r2 60.4k 1% keep power ground and signal ground separate. connect at one point. downloaded from: http:///
ltc3609 22 3609fb typical applications 5v to 32v input to 1.2v/6a at 550khz v out 1.2v at 6a gnd v in v in 5v to 32v c out1 100f x2 l1 0.8h c in 4.7f50v x2 ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 sgnd gnd v out pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc intv cc intv cc 32 intv cc pgood 31 sv in v in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 3609 ta03 c f 0.1f 25v r f1 1 c vcc 4.7f 6.3v extv cc c4 0.01f intv cc intv cc jp1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in c von 0.1f r160.4k 1% r pg1 100k r on 182k 1% r2 60.4k 1% r5 8.45k c c1 1500pf c c2 100pf v out c5: taiyo yuden jmk316bj226ml-t c in : murata grm32er71h475k c out : murata grm435r60j167m l i : cdep850r8mc-88 2 r30 keep power ground and signal ground separate. connect at one point. load current (a) 0.01 efficiency (%) 80 10 3609 ta02c 50 7570 65 60 55 0.1 1 9085 v in = 12v frequency = 550khz load step 1a to 6av in = 12v v out = 1.2v fcb = 0v 3609 ta02b 20s/div v out 200mv/div i l 5a/div transient response ef?ciency vs load current downloaded from: http:///
ltc3609 23 3609fb typical applications 5v to 32v input to 1.8v/6a all ceramic 1mhz v out 1.8v at 6a gnd v in v in 5v to 32v c out1 100f x2 l1 0.47h c in 4.7fx2 ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 sgnd gnd v out pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc intv cc intv cc 32 intv cc pgood 31 sv in v in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 3609 ta04 c f 0.1f 50v r f1 1 c vcc 4.7f 6.3v extv cc c4 0.01f intv cc intv cc jp1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in c von 0.1f r110k 1% r pg1 100k r on 102k 1% r2 20k 1% r5 5.76k c c1 1500pf c c2 100pf v out c5: taiyo yuden jmk316bj226ml-t c in : murata grm32er71h475k c out : murata grm32er60j107m l i : 1hlp25czerr80m01 2 keep power ground and signal ground separate. connect at one point. load current (ma) 10 efficiency (%) 80 10000 3609 ta04c 0 5040 30 20 10 7060 100 1000 100 90 load step 500ma to 4av in = 12v v out = 1.8v fcb = 0v 3609 ta04b 20s/div v out 200mv/div i l 5a/div transient response ef?ciency vs load current downloaded from: http:///
ltc3609 24 3609fb package description 7.00 bsc 8.00 bsc 15 19 26 bottom view (bottom metallization details) top view 0.90 0.10 // ccc c 0.00 ? 0.05 mlp52 qfn rev ? 0807 nx b seating plane 8 9 7 0.08 c aaa c aaa c m ac b bbb nx a b 2x 2x 41 18 9 10 27 4033 32 note:1. dimensioning and tolerancing conform to asme y14.5m-1994 2. all dimensions are in millimeters, angles are in degrees ( ) 3. n is the total number of terminals5. nd and ne refer to the number of terminals on each d and e side respectively 6. njr refer to non jedec registered 4 the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 spp-002 7 dimension b applies to metallized terminal and is measured between 0.20mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 8 coplanarity applies to the terminals and all other surface metallization 9 drawing shown are for illustration only symbol aaa bbb ccc tolerance 0.150.10 0.10 pad 1 corner recommended solder pad layout top view 0.50 bsc 2.025 0.10 2.925 0.10 pin 1 pin 1 id 1.00 ref 0.50 bsc 1.775 ref 7.50 0.05 8.50 0.05 packageoutline 2.25 0.10 0.25 0.05 0.40 0.10 3.20 0.10 3.40 ref 3.90 0.10 3.40 ref 1.00 ref 1.775 ref 4.275 0.10 2.625 ref 2.90 ref 1.35 0.10 2.25 0.10 0.25 0.05 0.40 0.10 14 52 2.025 0.10 2.925 0.10 4.275 0.10 3.20 0.10 3.40 ref 2.625 ref 2.90 ref 1.35 0.10 3.90 0.10 3.40 ref 0.580 0.10 4 wkg package 52-lead qfn multipad (7mm 8mm) (reference ltc dwg # 05-08-1768 rev ?) downloaded from: http:///
ltc3609 25 3609fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 06 /10 updated sw voltage range in absolute maximum ratings. note 4 updated. 24 (revision history begins at rev b) downloaded from: http:///
ltc3609 26 3609fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ?? linear technology corporation 2008 lt 0610 rev b ? printed in usa related parts typical application figure 8. 14v to 32v input to 12v/4a at 500khz v out 12v at 4a gnd v in v in 14v to 32v c out1 180f 16v l1 4.3h c in 4.7fx2 + ltc3609 sgnd 26 nc 25 nc 24 v fb 23 i on 22 nc 21 sgnd 20 fcb 19 i th 18 v rng 17 pgood 16 sgnd 15 sgnd gnd v out pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 sw sw sw sw 8 nc 9 sgnd 10 boost 11 run/ss 12 v on 13 sgnd 14 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 pgnd 34 sw 33 intv cc intv cc intv cc 32 intv cc pgood 31 sv in v in 30 extv cc 29 nc 28 sgnd 27 sw 41 sw 42 sw 43 sw 44 sw 45 sw 46 sw 47 pv in 48 pv in 49 pv in 50 pv in 51 pv in 52 3609 ta05 c f 0.1f 50v r f1 1 c vcc 4.7f 6.3v extv cc c4 0.01f intv cc intv cc jp1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in c von 0.1f r13.16k 1% r pg1 100k r on 1m 1% r2 60.4k 1% r5 24.3k c c1 1000pf c c2 100pf intv cc c in : murata grm31cr71h475k c out : sanyo 16svp180mx l i : cdep4r3mc-88 2 keep power ground and signal ground separate. connect at one point. part number description comments ltc3602 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 4.5v to 10v, v out(min) = 0.6v, i q = 75a, i sd <1a, 4mm 4mm qfn-20, tssop-16e packages ltc3608 18v, 8a (i out ), 1mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 4v to 18v, v out(min) = 0.6v, i q = 900a, i sd <15a, 7mm 8mm qfn-52 package ltc3610 24v, 12a (i out ), 1mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 4v to 24v, v out(min) = 0.6v, i q = 900a, i sd <15a, 9mm 9mm qfn-64 package ltc3611 32v, 10a (i out ), 1mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 4v to 32v, v out(min) = 0.6v, i q = 900a, i sd <15a, 9mm 9mm qfn-64 package ltc3414/ ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop20e package ltc3415 7a (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 450a, i sd <1a, 5mm 7mm qfn-38 package ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% eficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 380a, i sd <1a, 5mm 7mm qfn-38 package downloaded from: http:///

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